ISPSD2021 | The 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Technical Program of ISPSD2021

ISPSD2021 Program at a glance

ISPSD2021 Program at a glance

Opening session

Monday May 31, 2021

12:10-12:40

Chair
Kimimori Hamada(PDPlus LLC)
Ichiro Omura(Kyushu Institute of Technology)

Plenary sessions

Monday May 31, 2021

Plenary 1

12:40-14:00

Chair
Kimimori Hamada(PDPlus LLC)
Wai Tung Ng(University of Toronto)
12:40-13:20

PL1-1Automotive semiconductors in the CASE era

Yasushi Shinojima (MIRISE Technologies Corporation,Japan)

13:20-14:00

PL1-2GaN 2.0: Power FinFETs, Complementary Gate Drivers and Low-Cost Vertical Devices

Tomás Palacios (MIT, USA)

Plenary 2

14:20-15:40

Chair
Ichiro Omura(Kyushu Institute of Technology)
Kevin Chen(Hong Kong University of Science and Technology)
14:20-15:00

PL2-1Building Blocks of Past, Present and Future BCD Technologies

François Hébert (Global Foundries)

15:00-15:40

PL2-2How System Basis Chips rise to the power and reliability challenges for future-proof electrification and autonomous vehicle electronic control unit designs

Erwan Hemon (NXP)

Oral sessions

Tuesday June 01, 2021

Session 1: IGBTs
Venue: Nobunaga Room

12:10-13:25

Chair
Shigeto Honda(Mitsubishi Electric Corporation)
Yi Tang(Starpower Semiconductor)
12:10-12:35

1-1Self-Turn-on-Free 1200V Scaled CSTBT™ Driven by 5V Gate Voltage with Wide SOA

Koichi Nishi, Chen Ze, Koji Tanaka, Keisuke Eguchi, Takamasa Miyazaki, Akihiko Furukawa

(Mitsubishi Electric Corporation, Japan)

12:35-13:00

1-2Singular Point Source MOS Cell Concept (S-MOS) Implemented on a Narrow Mesa Trench IGBT

Munaf Rahimo1, Iulian Nistor1, David Green2

(1mqSemi AG, Switzerland; 2Silvaco Europe Ltd., United Kingdom)

13:00-13:25

1-3Low Switching Loss Diode of 600V RC-IGBT with New Contact Structure

Kenji Suzuki2, Takuya Yoshida1, Yuki Haraguchi2, Hidenori Koketsu2, Atsushi Narazaki2

(1Melco Semiconductor Engineering Corporation, Japan; 2Mitsubishi Electric Corporation, Japan)

Session 2: Dynamic Ron & Reliability of p-GaN Gate Technologies
Venue: Ieyasu Room

12:10-13:50

Chair
Grace Xing(Cornell University)
Yoshinao Miura(AIST)
12:10-12:35

2-1Impact Ionization Induced Breakdown and Related HTRB Behaviors in 100-V p-GaN Gate HEMTs

Yan Cheng, Yuru Wang, Sirui Feng, Zheyang Zheng, Tao Chen, Gang Lyu, Yat Hon Ng, Kevin Jing Chen

(The Hong Kong University of Science and Technology, China)

12:35-13:00

2-2A Bootstrap Voltage Clamping Circuit for Dynamic VTH Characterization in Schottky-Type p-GaN Gate Power HEMT

Kailun Zhong, Han Xu, Song Yang, Zheyang Zheng, Junting Chen, Kevin Jing Chen

(ECE Department, HKUST, Hong Kong)

13:00-13:25

2-3Surface Reinforcement Technology for Suppressing Hot-Carrier-Induced Degradations in p-GaN Gate Power HEMTs

Li Zhang, Song Yang, Zheyang Zheng, Wenjie Song, Hang Liao, Kevin Jing Chen

(The Hong Kong University of Science and Technology, China)

13:25-13:50

2-4Impact of OFF-State Gate Bias on Dynamic RON of p-GaN Gate HEMT-

Zuoheng Jiang2, Mengyuan Hua2, Xinran Huang2, Lingling Li2, Junting Chen2, Kevin Jing Chen1

(1Hong Kong University of Science and Technology, Hong Kong; 2Southern University of Science and Technology, China)

Session 3: Ics for High Efficiency & High Reliability
Venue: Nobunaga Room

13:45-15:50

Chair
Kenji Hara(Hitachi)
Nicolas Rouger(CNRS / Laplace)
13:45-14:10

3-1The On-Chip Lateral Super-Junction IGBT in Integrated High-Voltage Low-Power Converters

Christoph Rindfleisch1, Elizabeth Kho Ching Tee3, Alexander Hölke2, Bernhard Wicht1

(1Leibniz Universität Hannover, Germany; 2X-FAB Global Services GmbH, Germany; 3X-FAB Sarawak Sdn. Bhd., Malaysia)

14:10-14:35

3-25 V, 300 MSa/s, 6-Bit Digital Gate Driver IC for GaN Achieving 69 % Reduction of Switching Loss and 60 % Reduction of Current Overshoot

Ryunosuke Katada2, Katsuhiro Hata2, Yoshitaka Yamauchi2, Ting-Wei Wang1, Ryuzo Morikawa2, Cheng-Hsuan Wu2, Toru Sai2, Po-Hung Chen1, Makoto Takamiya2

(1National Chiao Tung University, Taiwan; 2University of Tokyo, Japan)

14:35-15:00

3-3A GaN-Based Active Diode Circuit for Low-Loss Rectification

Michael Basler1, Richard Reiner1, Stefan Moench1, Patrick Waltereit1, Rüdiger Quay1, Ingmar Kallfass2, Oliver Ambacher1

(1Fraunhofer Institute for Applied Solid State Physics IAF, Germany; 2University of Stuttgart, Germany)

15:00-15:25

3-4Gate Driver for p-GaN HEMTs with Real-Time Monitoring Capability of Channel Temperature

Alessandro Borghese, Michele Riccio, Luca Maresca, Giovanni Breglio, Andrea Irace

(University of Naples Federico II, Italy)

15:25-15:50

3-5A Smart Gate Driver for SiC Power MOSFETs with Aging Compensation and Ringing Suppression

Mengqi Wang2, Wei Jia Zhang2, Jingyuan Liang2, Wen Tao Cui2, Haruhiko Nishio1, Hitoshi Sumida1, Hiroyuki Nakajima1, Wai Tung Ng2

(1Fuji Electric Co., Ltd., Japan; 2University of Toronto, Canada)

Session 4: SiC Advanced Novel Devices
Venue: Ieyasu Room

14:10-15:50

Chair
Andrei Petru Mihaila(Hitachi ABB Power Grids)
Yasuhiko Onishi(Fuji Electric)
14:10-14:35

4-1First Demonstration of a Monolithic SiC Power IC Integrating a Vertical MOSFET with a CMOS Gate Buffer

Mitsuo Okamoto, Atsushi Yao, Hiroshi Sato, Shinsuke Harada

(AIST, Japan)

14:35-15:00

4-2The FinFET Effect in Silicon Carbide MOSFETs

Florin Udrea3, Kaloyan Naydenov3, Hyemin Kang3, Takehiro Kato2, Eiji Kagoshima2, Tsuyoshi Nishiwaki2, Hirokazu Fujiwara2, Tsunenobu Kimoto1

(1Kyoto University, Japan; 2MIRISE Technologies, Japan; 3University of Cambridge, United Kingdom)

15:00-15:25

4-3Improved Clamping Capability of Parasitic Body Diode Utilizing New Equivalent Circuit Model of SBD-Embedded SiC MOSFET

Teruyuki Ohashi1, Hiroshi Kono2, Souzou Kanie2, Takahiro Ogata2, Kenya Sano2, Hisashi Suzuki2, Shunsuke Asaba2, Shigeto Fukatsu1, Ryosuke Iijima1

(1Corporate Research & Development Center, Toshiba Corporation, Japan; 2Toshiba Electronic Devices & Storage Corporation, Japan)

15:25-15:50

4-4Ultra-Low Specific on-Resistance Achieved in 3.3 kV-Class SiC superjunction MOSFET

Masakazu Baba2, Takeshi Tawara2, Tadao Morimoto2, Manabu Takei1, Hiroshi Kimura1, Shinsuke Harada2

(1Fuji Electric Co., Ltd., Japan; 2National institute of Advanced Industrial Science and Technology, Japan)

Wednesday June 02, 2021

Session 5: Lateral Low Vltage Devices
Venue: Nobunaga Room

12:10-13:50

Chair
Tatsuya Nishiwaki(Toshiba Electronic Devices & Storage Corporation)
Hiroki Fujii(Samsung Electronics)
12:10-12:35

5-1Experimental Study of Ultralow On-Resistance Power LDMOS with Convex-Shape Field Plate Structure

Jie Wei2, Zhen Ma2, Xiaorong Luo2, Congcong Li2, Gaoqiang Deng2, Hua Song1, Kaiwei Dai2, Yanjiang Jia2, Dezun Liao2, Sen Zhang1, Bo Zhang2

(1CSMC Technologies Corporation, China; 2University of Electronic Science and Technology of China, China)

12:35-13:00

5-2Analysis of Anomalous Behavior During Negative Drain Input Operation of Fully Isolated nLDMOS

Atsushi Sakai, Katsumi Eikyu, Yotaro Goto, Makoto Koshimizu, Kenichiro Sonoda, Tamotsu Ogata

(Renesas Electronics Corp., Japan)

13:00-13:25

5-3Mitigation of Space-Charge-Modulation in 800-V JFET for HV Start-Up Circuit Toward High ON-BV Performance

Zhangyi'An Yuan2, Xinjian Li2, Ming Qiao2, Zhao Wang2, Ying Cai1, Feng Jin1, Jiye Yang1, Shuhao Zhang2, Dican Hou2, Xin Zhou2, Zhaoji Li2, Bo Zhang2

(1Shanghai Huahong Grace Semiconductor Manufacturing Corporation, China; 2University of Electronic Science and Technology of China, China)

13:25-13:50

5-4Low On-Resistance SOI-LDMOS with Mobility-Enhancing Auxiliary Cell

Jie Ma2, Long Zhang2, Yongjiu Cui2, Xinyu Liu2, Wangming Cui2, Jing Zhu2, Weifeng Sun2, Yan Gu1, Nailong He1, Sen Zhang1

(1CSMC Technologies Corporation, China; 2Southeast University, China)

Sesion 6: SiC Device Ruggedness & Reliability
Venue: Ieyasu Room

12:10-13:50

Chair
Siddarth Sundaresan(GeneSiC Semiconductor)
Hiroshi Kono(Toshiba Electronic Devices & Storage)
12:10-12:35

6-1Comprehensive Investigation on Electrical Properties of 4H-SiC VDMOS Under Uniaxial and Biaxial Mechanical Strains

Hongyu Wei, Wangran Wu, Pengyu Tang, Guangan Yang, Siyang Liu, Weifeng Sun

(Southeast University, China)

12:35-13:00

6-2Study of 1.2kV High-K SiC Power MOSFETs Under Harsh Repetitive Switching Conditions

Stephan Wirths, Andrei Mihaila, Gianpaolo Romano, Nick Schneider, Edoardo Ceccarelli, Giovanni Alfieri, Yulieth Arango, Lars Knoll

(Hitachi ABB Power Grids Ltd., Switzerland)

13:00-13:25

6-3Device Design to Achieve Low Loss and High short-Circuit Capability for SiC Trench MOSFET

Yuki Mori, Takeru Suto, Tomoka Suematsu, Haruka Shimizu, Naoki Watanabe, Hiroshi Miki, Digh Hisamoto, Toru Masuda, Akio Shima

(Hitachi, Ltd., Japan)

13:25-13:50

6-4Investigations of UIS Failure Mechanism in 1.2 kV Trench SiC MOSFETs Using Electro-Thermal-Mechanical Stress Analysis

Kailun Yao, Hiroshi Yano, Noriyuki Iwamuro

(University of Tsukuba, Japan)

Session 7: Packaging Technologies: Integrated Modeling & Design
Venue: Nobunaga Room

14:10-15:50

Chair
Tomoyuki Miyoshi(Hitachi)
Ichiro Omura(Kyushu Institute of Technology)
14:10-14:35

7-1Novel Monolithic Integrated Device with Gate Resistor for External IGBT Clamping Leading to Enhanced Short Circuit Behavior

Wolfgang-Michael Schulz, Matthias Spang, Arendt Wintrich, Bernhard König, Sven Berberich

(SEMIKRON Elektronik GmbH & Co. KG, Germany)

14:35-15:00

7-2Electrothermal Modeling, Simulation, and Electromagnetic Characterization of a 3.3 kV SiC MOSFET Power Module

Ciro Scognamillo3, Antonio Pio Catalano3, Alessandro Borghese3, Ravi Tripathi2, Michele Riccio3, Vincenzo D'Alessandro3, Lorenzo Codecasa1, Alberto Castellazzi2, Giovanni Breglio3, Andrea Irace3

(1Politecnico di Milano, Italy; 2Solid-State Power Processing SP2 Lab / Kyoto University of Advanced Science, Japan; 3University of Naples Federico II, Italy)

15:00-15:25

7-3Impact of Chip-Package-PCB Design on the Optimization of AC/DC Switched Mode Power Supply Using Time Domain Analysis

Bogdan Popescu2, Ivana Kovacevic-Badstuebner1, Dan Popescu2, Ulrike Grossner1

(1ETH Zurich, Switzerland; 2Infineon AG, Germany)

15:25-15:50

7-4A Direct Bond Fabrication Process for Compact GaN Intelligent Power Modules on Liquid Coolers for EV Applications

Namjee Kim2, Wei Jia Zhang2, Jingyuan Liang2, Wen Tao Cui2, Andrei Catuneanu1, Matthew Birkett1, John Burgers1, Wai Tung Ng2

(1Dana Canada Corporation, Canada; 2University of Toronto, Canada)

Session 8: Advances on Fin-FITs & Alternative p-type Materials for GaN Devices
Venue: Ieyasu Room

14:10-15:50

Chair
Jiun-Lei Yu(TSMC)
Hideyuki Okita(Panasonic)
14:10-14:35

8-1LiNiO Gate Dielectric with Tri-Gate Structure for High Performance E-Mode GaN Transistors

Taifang Wang, Mohammad Samizadeh Nikoo, Luca Nela, Elison Matioli

(École Polytechnique Fédérale de Lausanne, Switzerland)

14:35-15:00

8-2Kilovolt Tri-Gate GaN Junction HEMTs with High Thermal Stability

Yunwei Ma4, Ming Xiao4, Zhonghao Du3, Xiaodong Yan3, Kai Cheng1, Michael Clavel4, Mantu Hudait4, Lei Tao4, Feng Lin4, Ivan Kravchenko2, Han Wang3, Yuhao Zhang4

(1Enkris Semidonductor Inc., China; 2Oak Ridge National Laboratory, United States; 3University of South Carolina, United States; 4Virginia Polytechnic Institute and State University, United States)

15:00-15:25

8-3High-Performance Enhancement-Mode AlGaN/GaN Multi-Channel Power Transistors

Luca Nela1, Catherine Erine1, Jun Ma1, Halil Kerim Yildirim1, Remco van Erp1, Peng Xiang2, Kai Cheng2, Elison Matioli1

(1École Polytechnique Fédérale de Lausanne, Switzerland; 2Enkris Semidonductor Inc., China)

15:25-15:50

8-4p-NiO Junction Termination Extensions for High Voltage Vertical GaN Devices

Riyaz Abdul Khadar, Alessandro Floriduz, Taifang Wang, Catherine Erine, Remco van Erp, Luca Nela, Reza Soleimanzadeh, Pirouz Sohi, Elison Matioli

(École Polytechnique Fédérale de Lausanne, Switzerland)

Thursday June 03, 2021

Session 9: Simulation Analysis for Silicon Vertical Devices
Venue: Nobunaga Room

12:10-13:50

Chair
Yuichi Onozawa(Fuji Electric)
Takahiro Mori(Renesas Electronics Corp.)
12:10-12:35

9-1Design Optimization of Multiple Stepped Oxide Field Plate Trench MOSFETs with Machine Learning for Ultralow On-Resistance

Hiro Gangi1, Yasunori Taguchi1, Kouta Nakata1, Hiroki Nemoto1, Yusuke Kobayashi1, Tomoaki Inokuchi1, Kazuto Takao1, Kenya Kobayashi2

(1Toshiba Corporation, Japan; 2Toshiba Electronic Devices & Storage Corporation, Japan)

12:35-13:00

9-2Gate Drive Techniques of Gate-Connected Trench Field Plate Power MOSFETs to Reduce Both Switching and Conduction Losses

Tatsuya Nishiwaki, Tsuyoshi Kachi, Yusuke Kawaguchi, Shinichi Umekawa

(Toshiba Electronic Devices & Storage Corporation, Japan)

13:00-13:25

9-3Dynamic in-Chip Current Distribution Simulation Technology for Power Device Layout Design

Takashi Saito, Kenji Koba, Saburo Hojo, Toshiharu Chiba, Boyu Shi, Hajime Shimizu, Nao Nagata

(Renesas Electronics Corp., Japan)

13:25-13:50

9-41200V Bidirectional FS-IGBT (BFS-IGBT) with Superior turn-Off Capability

Masahiro Tanaka2, Naoki Abe2, Akio Nakagawa1

(1Nakagawa Consulting Office, LLC., Japan; 2Nihon Synopsys G.K., Japan)

Session 10: Packaging Technologies: Characterization & Reliability
Venue: Ieyasu Room

12:10-13:50

Chair
Alberto Castellazzi(Kyoto University of Advanced Science)
Yang Xu(Tesla)
12:10-12:35

10-1Improved DICM with an IR Camera for Imaging of Strain and Temperature in Cross Section of to Packages

Yoshiki Masuda, Akihiko Watanabe, Ichiro Omura

(Kyushu Institute of Technology, Japan)

12:35-13:00

10-2DUT Temperature Coefficient and Power Cycles to Failure

Yuma Kawauchi, Kenji Akimoto, Akihiko Watanabe, Ichiro Omura

(Kyushu Institute of Technology, Japan)

13:00-13:25

10-3Comparison of the Power Cycling Performance of Silicon and Silicon Carbide Power Devices in a Baseplate Less Module Package at Different Temperature Swings

Felix Hoffmann2, Stefan Schmitt1, Nando Kaminski2

(1Semikron Elektronik GmbH&Co. KG, Germany; 2University of Bremen, Germany)

13:25-13:50

10-4Development of Solder Deterioration Diagnosis System of a Power Module via the Acoustic Emission Monitoring (AEM) Technique

Zheng Zhang2, Aiji Suetake2, Chuantong Chen2, Hiroshi Ishino1, Hirokazu Sampei1, Takeshi Endo1, Kazuhiko Sugiura1, Kazuhiro Tsuruta1, Katsuaki Suganuma2

(1MIRISE Technologies, Japan; 2Osaka University, Japan)

Session 11: Vertical Low Voltage Devices
Venue: Nobunaga Room

14:10-15:25

Chair
Takahiro Mori(Renesas Electronics Corp.)
Mark Gajda(Nexperia)
14:10-14:35

11-1Integrated Termination Ballast to Mitigate Avalanche Hotspots in Trench Field Plate Power MOSFETs

Tanuj Saxena, Christian Torrent, Vishnu Khemka, Ganming Qin, Moaniss Zitouni

(NXP Semiconductors Inc., France; NXP Semiconductors Inc., United States)

14:35-15:00

11-2Stacked Chip of Si Power Device with Double Side Cu Plating for Low on-Resistance

Tatsuya Ohguro, Hideharu Kojima, Takuma Hara, Tatsuya Nishiwaki, Shinichi Umekawa

(Toshiba Electronic Devices & Storage Corporation, Japan)

15:00-15:25

11-3Drift Layer Design Utilizing Intermediate Boron Ion-Implantation for 100-V-Class Two-step-Oxide Field-Plate Trench MOSFET to Improve Switching Loss

Kenya Kobayashi, Hiroaki Kato, Kikuo Aida, Akihiro Goryu, Tatsuya Nishiwaki

(Toshiba Electronic Devices & Storage Corporation, Japan)

15:25-15:50

11-LNExperimental of Folded Accumulation Lateral Double-diffused Transistor with Low Specific On Resistance

Yandong Wang, Baoxing Duan, Yintang Yang

(Xidian University, China)

Closing session

Thursday June 03, 2021

15:50-16:10

Chair
Kimimori Hamada(PDPlus LLC)
Ichiro Omura(Kyushu Institute of Technology)

Poster Sessions

Poster Sessions will be held from 10:00 May 31, 2021 (JST) to 15:50 June 3, 2021 (JST)

Core Time
“IC Design” and “SiC Devices & Technologies” 16:10~17:40 May 31, 2021 (JST)
“Low Voltage Devices & Power IC Device Technology”
and “GaN Devices & Technology”
16:10~17:40 June 1, 2021 (JST)
“High Voltage Devices” and “Module & Package Technologies” 16:10~17:40 June 2, 2021 (JST)

IC Design

Chair
Xin Ming(University of Electronic Science and Technology)

ICD-P1Slope Sensing for Optimum Dynamic Gate Driving of SiC Power MOSFETs

Wen Tao Cui2, Wei Jia Zhang2, Jingyuan Liang2, Mengqi Wang2, Haruhiko Nishio1, Hitoshi Sumida1, Hiroyuki Nakajima1, Wai Tung Ng2

(1Fuji Electric Co., Ltd., Japan; 2University of Toronto, Cana)

ICD-P2Novel Integrated Low Capacitance Transient Voltage Suppressor Array with Capacitance Equalization Technique for System-Level EOS/ESD Protection

Zhao Qi, Ming Qiao, Fei Zhao, Zhaoji Li, Bo Zhang

(University of Electronic Science and Technology of China, China)

SiC Devices & Technology

Chair
Naruhisa Miura(Mitsubishi Electric)

SiC-P1Comparison of Short Circuit Robustness and Failure Mechanisms of GaN/SiC Cascode Devices and SiC Power MOSFETs

Jiahui Sun, Kailun Zhong, Zheyang Zheng, Gang Lyu, Kevin Jing Chen

(Hong Kong University of Science and Technology, China)

SiC-P21.2 kV 4H-SiC VDMOSFETs with Si-Implanted Surface: Performance Enhancement and Reliability Evaluation

Jia-Wei Hu3, Jheng-Yi Jiang3, Pin-Wei Huang3, Chih-Fang Huang3, Shun-Wei Tang1, Zhen-Hong Huang1, Tian-Li Wu1, Kung-Yen Lee2

(1National Chiao Tung University, Taiwan; 2National Taiwan University, Taiwan; 3National Tsing Hua University, Taiwan)

SiC-P3Comprehensive Study on Electrical Characteristics in 1.2 kV SiC SBD-Integrated Trench and Planar MOSFETs

Kevin Matsui2, Ruito Aiba2, Masakazu Baba1, Shinsuke Harada1, Hiroshi Yano2, Noriyuki Iwamuro2

(1Graduate School of Pure and Applied Sciences, University of Tsukuba, Japan; 2National Institute of Advanced Industrial Science and Technology, Japan)

SiC-P4Experimental and Numerical Demonstration of Superior RBSOAs in 1.2 kV SiC Trench and SBD-Integrated Trench MOSFETs

Shunki Todaka2, Kevin Matsui2, Ruito Aiba2, Masakazu Baba1, Shinsuke Harada1, Hiroshi Yano2, Noriyuki Iwamuro2

(1Graduate School of Pure and Applied Sciences, University of Tsukuba, Japan; 2National Institute of Advanced Industrial Science and Technology, Japan)

SiC-P5Avalanche Capability of 650-V Normally-Off GaN/SiC Cascode Power Device

Kailun Zhong, Jiahui Sun, Yuru Wang, Gang Lyu, Sirui Feng, Tao Chen, Kevin Jing Chen

(ECE Department, HKUST, Hong Kong)

SiC-P6Improving the Specific on-Resistance and short-Circuit Ruggedness tradeoff of 1.2-kV-Class SBD-Embedded SiC MOSFETs Through Cell Pitch Reduction and Internal Resistance

Hiroshi Kono2, Shunsuke Asaba2, Teruyuki Ohashi1, Takahiro Ogata2, Masaru Furukawa2, Kenya Sano2, Masakazu Yamaguchi2, Hisashi Suzuki2

(1Corporate Research & Development Center, Toshiba Corporation, Japan; 2Toshiba Electronic Devices & Storage Corporation, Japan)

SiC-P7Avalanche Reliability of planar-Gate SiC MOSFET with Varied JFET Region Width and its Balance with Characteristic Performance

Zhengyun Zhu, Na Ren, Hongyi Xu, Li Liu, Kuang Sheng

(Zhejiang University, China)

SiC-P8Performance and Robustness of 6500 V SiC DMOSFETs with Integrated MPS Diodes

Siddarth Sundaresan, Jaehoon Park, Vamsi Mulpuri, Ranbir Singh

(GeneSiC Semiconductor, United States)

SiC-P9Degradation Investigations on Asymmetric Trench SiC Power MOSFETs Under Repetitive Unclamped Inductive Switching Stress

Hao Fu, Jiaxing Wei, Xiaowen Yan, Hangbo Zhao, Zhaoxiang Wei, Hua Zhou, Weifeng Sun, Siyang Liu

(Southeast University, China)

SiC-P10Gate Oxide Reliability of 1.2 kV and 6.5 kV SiC MOSFETs Under Stair-Shaped Increase of Positive and Negative Gate Bias

Roman Boldyrjew-Mast, Sven Thiele, Nora Schöttler, Thomas Basler, Josef Lutz

(Chemnitz University of Technology, Germany)

SiC-P11Surge Current Capability Evaluation of 6.5kV SiC MOSFETs with 3D Cell Layouts

Kaloyan Naydenov2, Nazareno Donato2, Florin Udrea2, Andrei Mihaila1, Gianpaolo Romano1, Stephan Wirths1, Lars Knoll1

(1Hitachi ABB Power Grids Ltd., Switzerland; 2University of Cambridge, United Kingdom)

SiC-P12A Compact and Cost-Efficient Edge Termination Design for High Voltage 4H-SiC Devices

Tianxiang Dai, Luyang Zhang, Oliver Vavasour, Arne Renz, Qinze Cao, Vishal Shah, Philip Mawby, Marina Antoniou, Peter M. Gammon

(University of Warwick, United Kingdom)

SiC-P13Effect of gate-Source Bias Voltage and gate-Drain Leakage Current on the short-Circuit Performance of FTO-Type SiC Power MOSFETs

Frederic Richardeau2, Alessandro Borghese1, Alberto Castellazzi3, Andrea Irace5, Vanessa Chazal4, Gerald Guibaud4

(1Kyoto University of Adavanced Science / SP2-Lab, Japan; 2LAPLACE, University of Toulouse, CNRS, Toulouse INP, UPS, France; 3Solid-State Power Processing SP2 Lab / Kyoto University of Advanced Science, Japan; 4Thales Group, ITEC Lab, France; 5University of Naples Federico II, Italy)

SiC-P14Temperature Dependent Transient Threshold Voltage Hysteresis in SiC Power MOSFETs and Implications for Short Circuit Events

Elena Mengotti1, Enea Bianda1, David Baumann1, Eirinaios K. Papamichalis1, Andrei Mihaila2, Stephan Wirths2

(1ABB Switzerland Ltd., Switzerland; 2Hitachi ABB Power Grids Ltd., Switzerland)

SiC-P15Rugged Dynamic Behaviour of 3.3kV SiC Power MOSFETs with High-K Gate Dielectric

Gianpaolo Romano, Stephan Wirths, Andrei Mihaila, Yulieth Arango, Antoni Ruiz, Lars Knoll

(Hitachi ABB Power Grids Ltd., Switzerland)

SiC-P16Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology

Sundar Babu Isukapati3, Hua Zhang2, Tianshi Liu2, Emran Ashik1, Bongmook Lee1, Adam Morgan3, Woongje Sung3, Ayman Fayed2, Anant Agarwal2

(1North Carolina State University, United States; 2Ohio State University, United States; 3State University of New York Polytechnic Institute, United States)

Low Voltage Devices & Power IC Device Technology

Chair
Riccardo Depetro(STMicroelectronics)

LVT-P1Power Loss Reduction of Low-Voltage Power MOSFET by Combination of Assist Gate Structure and Gate Control Technology

Wataru Saito1, Shin-Ichi Nishizawa2

(1Kyushu Universitty, Japan; 2Kyushu University, Japan)

LVT-P2Robustness Enhancement of the Floating NBL BCD Architecture: Parasitics Suppression and Addition of Partially Isolated Diode for Localized Voltage Control

Moshe Agam, Jaroslav Pjenčák, Johan Janssens

(ON Semiconductor, United States; ON Semiconductor, Belgium; ON Semiconductor, Czech Rep.)

LVT-P3Machine-Learning Based TCAD Optimization Method for Next Generation BCD Process Development

Jaehyun Yoo, Yongwoo Jeon, Dawon Jung, Junhyuk Kim, Jisu Ryu, Ohkyum Kwon, Yongdon Kim, Kwangtea Kim, Kyuok Lee, Jeahyun Jung, Uihui Kwon, Daesin Kim

(Samsung Electronics Co., Ltd., Korea)

LVT-P4Low-Temperature Fabricated Amorphous Oxide Semiconductor Heterojunction Diode for Monolithic 3D Power Integration Applications

Xianda Zhou3, Lei Lu2, Kai Wang3, Yang Liu3, Johnny K.O. Sin1

(1Hong Kong University of Science and Technology, Hong Kong; 2Peking University, China; 3Sun Yat-Sen University, China)

LVT-P5A Cost Effective and Highly Manufacturable Approach to Extend a BCD 70V Technology to 200V

Weize Chen2, Jaroslav Pjenčák3, Moshe Agam2, Johan Janssens2, Rick Jerome1, Santosh Menon2, Mark Griswold2

(1Gresham, United States; 2ON Semiconductor, United States; 3Technology Development, Czech Rep.)

LVT-P6Addressing the Challenges of sub-50nm Channel LDMOS

Brendan Toner4, Christoph Ellmers2, Stefan Eisenbrandt3, Zhengchao Liu4, Darin Davis1, Gary Dolny1, Terry Johnson1, William Richards1

(1Silicet Inc., United States; 2X-FAB Dresden Verwaltungs-GmbH, Germany; 3X-FAB Global Services GmbH, Germany; 4X-FAB Sarawak Sdn. Bhd., Malaysia)

LVT-P7On Precise Current Sensors for Low Voltage Trench MOSFETs

Radim Spetik, Justin Yerger, Ladislav Seliga, Filip Kudrna, Santosh Menon, Bruce Greenwood

(ON Semiconductor, Czech Rep.; ON Semiconductor, United States)

LVT-P8An Improved Negative Transient Voltage Noise Immunity for an HVIC Using Self-Shielding Structure

Akihiro Jonishi, Masaharu Yamaji, Takahide Tanaka, Hitoshi Sumida

(Fuji Electric Co., Ltd., Japan)

LVT-P9Investigation on the Single-Event Burnout and Hardening of the 500V SOI Lateral-IGBT

Yiwen Qian, Wangran Wu, Guangan Yang, Jing Yang, Long Zhang, Weifeng Sung

(Southeast University, China)

LVT-P10Reverse Recovery and Carrier Lifetime in Body Diodes of LDMOS Transistors

Vin Loong Choo1, Martin Pfost1, Jörg Gessner2, Klaus Heinrich2, Uwe Eckoldt2, Madelyn Liew3, Yang Hao3

(1TU Dortmund University, Germany; 2X-FAB Global Services GmbH, Germany; 3X-FAB Sarawak Sdn. Bhd., Malaysi)

LVT-P11Figure-of-Merit for Laterally Diffused MOSFETs with Rectangular and Semi-Circular Field Oxides

Ali Saadat2, Maarten Van de Put2, Hal Edwards1, William Vandenberghe2

(1Texas Instrument Inc., United States; 2University of Texas at Dallas, United States)

LVT-P12Study of Unique ESD Tolerance Dependence on Backgate Ratio for RESURF LDMOS with Rated Voltage Variation

Kanako Komatsu, Koichi Ozaki, Fumio Takeuchi, Daisuke Shinohara, Tomoko Kinoshita, Yoshiaki Ishii, Toshihiro Sakamoto, Fumitomo Matsuoka

(Toshiba Electronic Devices & Storage Corporation, Japan)

GaN Devices & Technology

Chair
Sameh Khalil(Infineon Technologies)

GaN-P1In Depth TCAD Analysis of Threshold Voltage on GaN-on-Si MOS-Channel Fully Recessed Gate HEMTs

Marie-Anne Jaud1, William Vandendaele1, Bledion Rrustemi1, Abygaël G. Viey1, Simon Martin1, Cyrille Le Royer1, Laura Vauche1, Sébastien Martinie1, Erwan Morvan1, Romain Gwoziecki1, Roberto Modica2, Ferdinando Iucolano2

(1CEA-LETI, France; 2STMicroelectronics, Italy)

GaN-P2Characteristics of Hetero-Integrated GaN-HEMTs on CMOS Technology by Micro-Transfer-Printing

Richard Reiner1, Ralf Lerner4, Patrick Waltereit1, Nis Hauke Hansen4, Stefan Moench1, Alin Fecioru3, David Gomez2

(1Fraunhofer Institute for Applied Solid State Physics IAF, Germany; 2X-Celeprint Inc, United States; 3X-Celeprint Ltd, Ireland; 4X-FAB Global Services GmbH, Germany)

GaN-P3Determination of Hard- and Soft-Switching Losses for Wide Bandgap Power Transistors with Noninvasive and Fast Calorimetric Measurements

Julian Weimer, Dominik Koch, Ruben Schnitzler, Ingmar Kallfass

(University of Stuttgart, Germany)

GaN-P4High Performance Quasi-Vertical GaN Junction Barrier Schottky Diode with Zero Reverse Recovery and Rugged Avalanche Capability

Feng Zhou2, Weizong Xu2, Fangfang Ren2, Dunjun Chen2, Rong Zhang2, Youdou Zheng2, Tinggang Zhu1, Hai Lu2

(1CorEnergy Semiconductor Co. Ltd., China; 2Nanjing University, China)

GaN-P5Investigation of GaN-on-Si and GaN-on-SOI Substrate Capacitances for Discrete and Monolithic Half-Bridges

Stefan Moench1, Richard Reiner1, Patrick Waltereit1, Rüdiger Quay1, Oliver Ambacher1, Ingmar Kallfass2

(1Fraunhofer Institute for Applied Solid State Physics IAF, Germany; 2University of Stuttgart, Germany)

GaN-P6Threshold Voltage Engineering in Al2O3/AlGaN/GaN MISHEMTs with Thin Barrier layer: MIS-Gate Charge Control and High Threshold Voltage Achievement

Liang He3, Liuan Li2, Jialin Zhang1, Yiqiang Ni1, Jinwei Zhang2, Zhenxing Liu2, Qianshu Wu2, Yang Liu2

(1No.5 Electronics Research Institute of the Ministry of Industry and Information Technology, China; 2Sun Yat-Sen University, China; 3Sun Yat-Sen University/No.5 Electronics Research Institute of the Ministry of Industry & Information, China)

GaN-P7A New JTE Technique for Vertical GaN Power Devices by Conductivity Control Using Boron Implantation Into p-Type Layer

Yoshinao Miura, Hirohisa Hirai, Akira Nakajima, Shinsuke Harada

(AIST, Japan)

High Voltage Devices

Chair
Noriyuki Iwamuro(University of Tsukuba)

HV-P1RC-GID IGBT – A Novel Reverse-Conducting IGBT with a Gate Voltage Independent Diode Characteristic and Low Power Losses

Quang Tien Tran2, Franz-Josef Niedernostheide1, Frank Pfirsch1, Anton Mauder1, Roman Baburske1, Hans-Günter Eckel2

(1Infineon Technologies AG, Germany; 2University of Rostock, Germany)

HV-P2Study About FZ/MCZ Si Wafer (Mother) Material Carbon and Oxygen Density for RC-IGBT with Electron Beam Irradiation Based on Electrical and Physical Analysis

Haruhiko Minamitake2, Takuya Yoshida1, Kenji Suzuki2, Yuki Haraguchi2, Taiki Hoshi2, Hidenori Koketsu2, Yusuke Miyata2, Atsushi Narazaki2

(Mitsubishi Electric Corporation, Japan)

HV-P3Depletion MOS Controlled Current Regulator Diode Based on Bipolar Carrier Transport

Ming Qiao2, Yong Chen2, Dican Hou2, Linrong He2, Peipei Meng2, Sen Zhang1, Zhaoji Li2, Bo Zhang2

(1CSMC Technologies Corporation, China; 2University of Electronic Science and Technology of China, China)

HV-P4Snap-Back Free 3.3kV RC-IGBT with Enhanced Safe Operating Area

Tanya Trajkovic1, Vasantha Pathirana1, Nishad Udugampola1, Florin Udrea1, Chunlin Zhu2, Yangang Wang2

(1Cambridge Microelectronics Ltd, United Kingdom; 2Dynex Semiconductor Ltd, United Kingdom)

HV-P5Ultra-Low Switching Loss Triple-Gate Controlled IGBT

Tatsunori Sakano1, Kazuto Takao1, Yoko Iwakaji2, Hiroko Itokazu2, Tomoko Matsudai2

(1Toshiba Corporation, Japan; 2Toshiba Electronic Devices & Storage Corporation, Japan)

HV-P6Benchmarking of Digital Gate Driven IGBTs: New Eoff-Vsurge Trade-Off Approach

Kouji Harasaki, Masanori Tsukuda, Ichiro Omura

(Kyushu Institute of Technology, Japan)

Module & Package Technologies

Chair
Wei-Chung Lo(Industrial Technology Research Institute (ITRI))

PK-P1Investigation on the Impact of Environmental Stress on the Thermo-Mechanical Reliability of IGBTs by Means of Consecutive H3TRB and PCT Testing

Felix Hoffmann2, Stefan Schmitt1, Nando Kaminski2

(1Semikron Elektronik GmbH&Co. KG, Germany; 2University of Bremen, Germany)

PK-P2Influence of Low Junction Temperature Swing on the Power Cycling Lifetime of Bond Wire

Jie Chen, Erping Deng, Zixuan Zhao, Yongzhang Huang

(North China Electric Power University, China)

PK-P3Practical Limits of Liquid Cooling Electric Vehicle Power Modules

Andrei Catuneanu1, John Burgers1, Pascal Fleury2, Wei Jia Zhang3, Wai Tung Ng3

(1Dana Canada Corporation, Canada; 2Dana TM4, Canada; 3University of Toronto, Canada)

PK-P4A 48 V, 300 kHz, High Current DC/DC-Converter Based on Paralleled, Asymmetrical & Thermally Optimized PCB Embedded GaN Packages with Integrated Temperature Sensor

Dominik Koch2, Ankit Sharma1, Julian Weimer2, Mathias Weiser2, Till Huesgen1, Ingmar Kallfass2

(1University of Applied Science Kempten, Germany; 2University of Stuttgart, Germany)

PK-P5Low Temperature Cu Sinter Joining on Different Metallization Substrates and its Reliability Evaluation with a High Current Density

Chuantong Chen2, Aya Iwaki2, Aiji Suetake2, Kazuhiko Sugiura1, Kiyoshi Kanie3, Katsuaki Suganuma2

(1MIRISE Technologies, Japan; 2Osaka University, Japan; 3Tohoku University, Japan)

PK-P6Transient Stability Analysis of Discrete and Multi-Chip Power Semiconductor Packages

Dan Popescu2, Ivana Kovacevic-Badstuebner1, Bogdan Popescu2, Ulrike Grossner1

(1ETH Zurich, Switzerland; 2Infineon AG, Germany)

PK-P7Ultra-Low Loss on-Chip Magnetic Inductors in the far-BEOL for High Frequency Power Electronics

Syed Moham Zishan Ali2, Lulu Peng2, Patrick Rohlfs1, Yong Chau Ng2, Lothar Lehmann1, Chor Shu Cheng2, Lawrence Selvaraj2, Marcel Wieland1

(1GLOBALFOUNDRIES Dresden, Germany; 2GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore)

PK-P8Design for Reliability of SiC Multichip Power Modules: the Effect of Variability

Salvatore Race, Thomas Ziemann, Ivana Kovacevic-Badstuebner, Roger Stark, Shweta Tiwari, Ulrike Grossner

(ETH Zürich, Switzerland)