GaN 2.0: Power FinFETs, Complementary Gate Drivers and Low-Cost Vertical Devices
Tomás Palacios is a Professor in the Department of Electrical Engineering and Computer Science at MIT. He received his PhD from the University of California - Santa Barbara in 2006, and his undergraduate degree in Telecommunication Engineering from the Universidad Politécnica de Madrid (Spain). His current research focuses on demonstrating new electronic devices and applications for novel semiconductor materials such as graphene and gallium nitride. His work has been recognized with multiple awards including the Presidential Early Career Award for Scientists and Engineers, the 2012 and 2019 IEEE George Smith Award, and the NSF, ONR, and DARPA Young Faculty Awards, among others. Prof. Palacios is Chief Advisor and co-founder of Cambridge Electronics, Inc. He is a Fellow of IEEE.
Gallium Nitride (GaN) power transistors are quickly enabling a new generation of power electronic systems capable of operating at much higher power densities and efficiencies than their silicon counterpart. However, in spite of the excellent performance reported so far and their commercial success, today’s GaN power devices are only starting to scratch the surface of GaN’s ultimate potential. This talk will discuss some of the new technologies that are currently being developed on 8”wafers to significantly improve the performance and impact of GaN-based power electronics.
First, we will discuss how the fabrication of fins under the gate and/or access regions of lateral GaN transistors and diodes helps to significantly improve the modulation efficiency of these devices, at the same time that it provides new design flexibility to engineer the different input and output capacitances. These structures, when combined with either gate recesses or p-GaN layers make for almost ideal n-channel lateral power transistors.
To take full advantage of the reduced capacitance and high operating frequencies of GaN power electronics, it is necessary to minimize parasitic inductances between the power switches and the gate driver circuit. For this, the GaN community has traditionally leveraged enhancement-mode/depletionmode logic to integrate relatively simple gate-driver circuits on the same chip than the GaN power devices, however this technology suffers from significant power consumption and limited circuit design flexibility. To overcome these issues, we have developed a new all-GaN complementary technology that allows for the integration of high-performance n-channel and p-channel GaN enhancement-mode transistors on the same chip without the need of epitaxial regrowth or special processing. The key trade-offs of this technology will be discussed, as well the roadmap and initial performance results of integrated drivers and circuits.
Although lateral GaN devices have demonstrated excellent performance for breakdown voltages below 1200 V and current levels up to, approximately 20 A, their capability at higher voltages and currents is limited by the large area needed by the depletion region, and the difficult current extraction in lateral devices. Vertical transistors can overcome these two challenges, at the same time than they enjoy more uniform heat generation and potentially better reliability thanks to an improved control of the peak electric field far away from the semiconductor surface. Here we will review several vertical GaN structures fabricated on bulk GaN, Silicon wafers, or engineered QST substrates, and benchmark them in terms of performance and cost.
Finally, the talk will conclude with a discussion on the future roadmap for GaN-based power devices,and how it compares to the one of current and future contenders, such as SiC, Ga2O3, AlGaN, AlN and diamond. This comparison will put in perspective how the GaN power electronics revolution is just starting, and the exciting road ahead.