ISPSD 2021 The Ohmi Best Paper Award
First Demonstration of a Monolithic SiC Power IC Integrating a Vertical MOSFET with a CMOS Gate Buffer
Mitsuo Okamoto, Atsushi Yao, Hiroshi Sato, Shinsuke Harada
Abstract—In this study, we have realized a monolithic silicon carbide (SiC) power integrated circuit (IC) integrating a 1.2 kV-class trench gate vertical metal-oxide-semiconductor field-effect transistor (MOSFET) and a complementary metal-oxide-semiconductor (CMOS) gate buffer aiming to enhance the fast switching by eliminating the parasitic effects caused by external interconnections. The p-MOSFETs in SiC CMOS were balanced with n-MOSFETs using an epitaxial buried channel structure. The integrated SiC CMOS gate buffer allowed to control the vertical power MOSFET successfully. A breakdown voltage of around 1500 V was obtained, and a switching operation at 600 V and 10 A was achieved with a rise time of 24 ns and fall time of 28 ns.
Mitsuo Okamoto received the B.E., M.E., and Ph.D. degrees from Osaka University, Osaka, Japan, in 1996, 1998, and 2001, respectively. He is currently a senior researcher with Advanced Power Electronics Research Center, National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan. His current research interests include SiC MOS Physics and SiC CMOS integrated circuit technologies.
Atsushi Yao received Ph.D. degree from Kyoto University in 2015. He was a postdoctoral researcher at Kyoto University and Toyota Technological Institute from 2015 to 2016 and 2016 to 2018, respectively. He was an assistant professor at Toyama Prefectural University from 2018 to 2020. He is currently a researcher at National Institute of Advanced Industrial Science and Technology (AIST), Japan. His main research interests are power electronics and electrical motor.
Hiroshi Sato received the M.E. degree from Tokyo Metropolitan University in 1991. In 1991, he joined Electrotechnical laboratory. He received his Ph.D. degree from Science University of Tokyo in 1998. He is currently a team leader with National Institute of Advanced Industrial Science and Technology. His current interest is SiC power modules that operate at high temperature with high speed switching.
Shinsuke Harada received the B.E., M.E., and Ph.D. degrees from Kyushu University, Fukuoka, Japan, in 1995, 1997, and 2000, respectively. He is currently a team leader with National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan. His current research interests include widegap semiconductor power device technologies.
*The Ohmi Best Paper Award is awarded to the authors of a paper determined to be the best overall among all presented papers.
ISPSD 2021 The Charitat Award
High-Performance Enhancement-Mode AlGaN/GaN Multi-Channel Power Transistors
Luca Nela1, Catherine Erine1, Jun Ma1, Halil Kerim Yildirim1, Remco van Erp1, Peng Xiang2, Kai Cheng2, Elison Matioli1
(1École Polytechnique Fédérale de Lausanne, Switzerland; 2Enkris Semiconductor Inc., China)
Abstract—AlGaN/GaN devices have shown outstanding potential for power conversion applications. However, despite the recent progress, their performance is still far from what the material can offer in terms of on-resistance and breakdown voltage. To address this challenge, here we demonstrate a multi-channel tri-gate High-Electron-Mobility Transistor (HEMT) based on an AlGaN/GaN multiple channel heterostructure and a nanostructured gate region, The multi-channel heterostructure leads to a significantly reduced sheet resistance while the nanostructured gate provides excellent control over all the embedded channels and enables to effectively manage the large off-state electric fields. This approach results in e-mode devices with a threshold voltage (VTH) of 0.85 V at 1 µA/mm, very low specific on-resistance of 0.46 mOhm.cm2, and a large breakdown voltage of 1300 V. In addition, we demonstrate multi-channel devices with excellent VTH stability and reduced current collapse thanks to a novel conformal passivation technique, which shows the potential of the multi-channel tri-gate technology for future power conversion applications.
Luca Nela received his B.S. degree in Physical Engineering from Politecnico di Torino, Turin, Italy, in 2015. He then participated in a double degree program between Politecnico di Torino and Université Paris Diderot, Paris, France, from which he received his M.S. in Nanotechnologies for the ICTs and Quantum Devices in 2017. Finally, he joined the Power and Wide-Band-Gap Electronics Research Laboratory in EPFL, Lausanne, Switzerland, where he is currently pursuing a doctoral degree. His research interests include the design and characterization of power semiconductor devices.
*The Charitat Award is awarded to the young researcher who is less than 30 years old and both a first author and presenter of a paper determined to be the best overall among all eligible papers.
ISPSD 2021 The Best Poster Award
Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology
Sundar Babu Isukapati1, Hua Zhang3, Tianshi Liu3, Emran Ashik2, Bongmook Lee2, Adam Morgan1, Woongje Sung1, Ayman Fayed3, Anant Agarwal3
(1College of Nanoscale Science and Engineering, State University of New York Polytechnic Institute, Albany, NY, USA, 2Dept. of Elect. & Computer Eng., North Carolina State University, Raleigh, NC, USA, 3Dept. of Elect. & Computer Eng., The Ohio State University, Columbus, OH, USA)
Abstract—This paper reports the design and process flow for monolithic integration of lateral high voltage (HV) power MOSFET with low voltage (LV) CMOS circuits for SiC Power IC technology. The reported devices and circuits are fabricated on a N-/N+ 4H-SiC substrate at 150mm, production grade-Analog Devices Inc. (ADI) Hillview fabrication facility located in San Jose. The static performance characteristics of HV NMOS and LV CMOS are reported. For future high temperature applications, the static performances are fully characterized and are reported up to 200℃. Finally, to validate the fabricated CMOS, a 5-stage ring oscillator is also demonstrated.
*The Best Poster Award is awarded to the authors of a paper determined to be the best overall among all poster presentation papers.